The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory addressing.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory, such as DRAM (dynamic random-access memory), ROM (read-only memory) and EEPROM (electrically erasable programmable read-only memory). EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased in blocks instead of one address at a time. Programming can occur on an address-by-address basis. A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at high speeds. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. SDRAM controllers often scramble the addresses provided to the memory. In a volatile memory, address scrambling does not create a problem. In a non-volatile memory, however, scrambled addresses can result in erroneous operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory which can operate in a system having address scrambling.
The above-mentioned problems with non-volatile memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory comprises a plurality of address input connections, and an address de-scrambler circuit coupled to the plurality of address connections. The address de-scrambler circuit re-routes signals received on the plurality of address input connections to internal address circuitry.
In another embodiment, a flash memory comprises an array of non-volatile memory cells arranged in erasable blocks, address circuitry to access the array, a plurality of external address connections, and an address de-scrambler circuit coupled to the plurality of address input connections. The address de-scrambler circuit re-routes signals received on the plurality of external address connections to the address circuitry.
A method of accessing a flash memory comprises receiving scrambled address signals, de-scrambling the address signals, and accessing the memory using the de-scrambled addresses.